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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:15:21 11/06/2010 
-- Design Name: 
-- Module Name:    FF - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FF is
    Port ( fin : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           fout : out  STD_LOGIC;
			  clk : in STD_LOGIC);
end FF;

architecture Behavioral of FF is
begin
-- purpose : Implements a standard synchronous Flip-Flop working on the clock's falling edge.
PSYNCH: process(clk, reset)
begin
    if (clk'event and clk = '0') then
	   if reset = '1' then 
		      fout <= '0';
		else
		      fout <= fin;
	   end if;
    end if;
end process;
	 
end Behavioral;

